DfM&Y 2007 - Call for Participation

CALL FOR PARTICIPATION

Overview -- Advance Program -- Registration-- Additional Information -- Committees

Overview

Increased manufacturing variability in leading-edge process technologies requires new paradigms and solution technologies for yield optimization. SoC manufacturability and yield entails design-specific optimization of the manufacturing, and thus enhanced communications across the design-manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) methodologies and tools have been proposed in recent years. Some of these tools are leveraged during back-end design, others are applied post-GDSII (just before manufacturing handoff), and still others are applied post-design, from reticle enhancement and lithography through wafer sort, packaging, final test and failure analysis. DFM and DFY can dramatically impact the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using DFM and DFY solutions is an investment, and choosing the most cost effective one(s) requires careful analysis of integration and schedule overheads, versus quantified benefits. This workshop analyzes this key trend and its challenges, and provides an opportunity to discuss a range of DFM and DFY solutions for today’s SoC designs.

Advance Program

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Thursday -- Friday

October 25, 2007 (Thursday)

4:00 PM - 5:00 PM	OPENING SESSION
	Welcoming Remarks General Chair – Yervant Zorian, Virage Logic Program Chair – Andrew B. Kahng, UC San Diego
	Plenary Talk P.1. The IMPACT Research Program at the University of California – Addressing DFM&Y at 22nm Prof. Kameshwar Poolla, UC Berkeley
	Plenary Talk P.2. Regular Structures and the New DFM Wave Prof. Andrzej Strojwas, PDF Solutions and CMU

5:00 PM - 7:00 PM	SESSION 1: CONNECTING TEST & DIAGNOSIS TO YIELD OPTIMIZATION
	1.1 On the Correlation between Yield and DFM through Diagnosis M. Sonza Reorda, P. Bernardi, F. Melchiori, R. Sirtori, V. Tancorre, and D. Appello, Politecnico di Torino and STMicroelectronics, Italy
	1.2 Bridging Test, Diagnosis and DFM Anne Gattiker, IBM Corporation
	1.3 Yield Acceleration based on Programmable Test & Diagnosis Y. Zorian, G. Torjyan, D. Nenni, H. Nalbandian, Virage Logic
	1.4 Mixed Test Structure for Soft and Hard Defect Detection Jean-Michael Portal, Laboratoire Materiaux et Microelectronique
	1.5 A Built-In Self-Repair for NAND Flash Memory Yu-Ying Hsiao and Cheng-Wen Wu, National Tsing Hua University
	1.6 A Redesign Technique to Improve Manufacturing Yield by Exploiting Error Tolerance Doochul Shin and Sandeep K. Gupta, University of Southern California

7:00 PM - 9:00 PM	EVENING RECEPTION

October 26, 2007 (Friday)

8:00 AM - 10:00 AM	SESSION 2: PHYSICAL DESIGN AND MANUFACTURABILITY VERIFICATION
	2.1 DFM Optimization of Standard Cells Core Libraries Fabio Melchiori and Roberto Sirtori, STMicroelectronics
	2.2 Regularity-Enhanced Layout of Standard Cells Hidetoshi Onodera and Hiroaki Muta, Kyoto University
	2.3 VariTamer: A Heterogeneous Platform for Deciding the Best Layout Placement in Physical Implementation Jwu-E Chen, H.W. Huang, C.Y. Ho, and H.C. Liang, National Central University and Chung Yuan Christian University, Taiwan
	2.4 Via-Configurable Transistor Array: A Regular Design Technique to Improve ICs Yield Marc Pons, Francesc Moll, and Antonio Rubio, Universitat Politecnica de Catalunya and Intel Barcelona
	2.5 Flexible Model-Based DRC and DFM Verification Fedor G. Pikus, Mentor Graphics, Inc.
	2.6 Design-Intent OPC Shayak Banerjee, Praveen Elakkumanan, James Culp, Lars Liebmann, and Michael Orshansky, IBM East Fishkill and University of Texas at Austin

10:30 AM - 12:00 PM	SESSION 3 (INVITED): DFM&Y FUTURES FOR EDA
	3.1 Physical Signoff -- Bringing DFM Signoff into the Flow John Lee, Magma Design Automation
	3.2 DFM: From Buzz to Norm Joe Sawicki, Mentor Graphics
	3.3 How to Push Polygons to the Limit and Still Yield Dipu Pramanik, Cadence Design Systems

1:00 PM - 3:00 PM	SESSION 4: VARIABILITY AND YIELD
	4.1 A Designer's Approach to Modeling Process Variability Dejan Markovic, UCLA EE Department
	4.2 DFM Technology Roadmap Including Dimensional Variability Juan Antonio Carballo, Praveen Elakkumanan, and Sani Nassif, Argon Venture Partners, IBM East Fishkill, and IBM Austin Research Laboratory
	4.3 A Systematic Variation Aware Circuit Simulation Engine Shayak Banerjee, Praveen Elakkumanan, Duresti Chidambarrao, James Culp, Saibal Mukhopadhyay, and Michael Orshansky, University of Texas at Austin and IBM East Fishkill
	4.4 Statistics and Digital Design: Exploiting the Corners Kambiz Samadi, Mark Nakamoto, and Riko Radojcic, UC San Diego and Qualcomm CDMA Technologies
	4.5 Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fittings Lerong Cheng, Jinjun Xiong, and Lei He, UCLA and IBM Research
	4.6 On the Opportunity to Improve System Yield with Multi-Core Architectures Yury Markovsky and John Wawrzynek, University of California, Berkeley

3:00 PM - 5:00 PM	PANEL: From David to Goliath: The Role of Startups in the Evolution of DFM
	Organizer/Moderator: Juan-Antonio Carballo, Argon Venture Partners Panelists: Bob Gleason, Luminescent Ahmet Karakas, Gauda Frank Schellenberg, Mentor Graphics Atul Sharan, Cadence Clive Wu, Blaze DFM

Registration

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For more information on registration please visit the online registration.

Additional Information

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General Information

Yervant Zorian
Virage Logic Corp
Tel: +1-510-360-8035
Fax: +1-510-360-8078
E-mail: yzorian@computer.org

Committees

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General Chair
Yervant Zorian, Virage Logic

Program Chair
Andrew B. Kahng, UCSD/Blaze DFM

Publication
A. Ivanov, Univ British Columbia

Panels
J.-A. Carballo, Argon Capital

Finance
R. Aitken, ARM

Publicity
D. Gizopoulos, Univ Piraeus
K. Samadi, UC San Diego

Program Committee to include
D. Appello, STMicroelectronics
C. Bittlestone, Texas Instruments
A. Gattiker, IBM
P. Gupta, Blaze DFM
S. Hector, Freescale
K.S. Kim, Intel
F. Kurdahi, UC Irvine
H. Lee, Magma
A. Markosian, Ponte Solutions
D. Maynard, IBM
C. Metra, Univ of Bologna
M. Murakata, STARC
S. Nassif, IBM
M. Nicolaidis,TIMA
NS Nagaraj, Texas Instruments
M. Orshansky, Univ of Texas
V. Pitchumani, Intel
J.M. Portal, Univ of Marseilles
P. Prinetto, Politecnico di Torino
R. Radojcic, Qualcomm
J. Rey, Mentor Graphics
K. Roy, Purdue Univ
J. Segal, Spansion
A. Singh, Auburn Univ
D. Sylvester, Univ of Michigan
V. Vardanian, Virage Logic
B. Vermeulen, NXP
D.M.H. Walker, Texas A&M Univ
S. Wigley, LTX
C-W. Wu, National Tsing Hua Univ
H-J. Wunderlich, Univ of Stuttgart
G. Yeric, Synopsys

For more information, visit us on the web at: http://vlsicad.ucsd.edu/DFMY2007/

The 2nd IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y 2007) is sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC) and in cooperation with the IEEE Council on Electronic Design Automation (CEDA).